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Commit 8b156579 authored by philiyao's avatar philiyao
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added unfinished controller code

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///////////////////////////////////////////////////////////////////////////////////////////////////
// Company: <Name>
//
// File: Controller.v
// File history:
// <Revision number>: <Date>: <Comments>
// <Revision number>: <Date>: <Comments>
// <Revision number>: <Date>: <Comments>
//
// Description:
//
// <Description here>
//
// Targeted device: <Family::SmartFusion> <Die::A2F200M3F> <Package::484 FBGA>
// Author: <Name>
//
///////////////////////////////////////////////////////////////////////////////////////////////////
//`timescale <time_units> / <precision>
`define controller_addr 0x4005020
`define controller_get_data 0x4005024
`define controller_command 0x4005028
module Contoller(
input PCLK,
input PSEL,
input PRESERN,
input PENABLE,
output wire PREADY,
output wire PSLVERR,
input PWRITE,
input [31:0] PADDR,
input wire [31:0] PWDATA,
output wire [31:0] PRDATA,
output reg ControllerClk
output reg commandLine
input reg dataLine
output FABINT,
);
assign PSLVERR = 0;
assign PREADY = 1;
//PWDATA = 1 to start a transaction
assign wire start_transaction = (PADDR == controller_addr) && (PWDATA[0] == 1) && PWRITE && PSEL && PENABLE;
assign wire read_shift_register = (PADDR == controller_addr) && ~PWRITE && PSEL;
reg[31:0] shiftRegister = 0;
reg[31:0] clockDivider = 0;
reg[7:0] getSendCtr = 0;
always@ (posedge PCLK) begin
if (read_shift_register) begin
PRDATA <= shiftRegister;
end
if (start_transaction) begin
if (clockDivider >= 32'd100)
begin //100*2*500=100000
ControllerClk <= ~ControllerClk;
clockDivider <= 0;
else begin
clockDivider <= clockDivider + 1;
end
end
end
always@ (posedge ControllerClk) begin
getSendCtr <= getSendCtr + 1;
if (getSendCtr == 1'b1)
commandLine <= 1'b1;
else if ((getSendCtr > 1'b1) && (getSendCtr <= 3'b8))
commandLine <= 1'b0;
if (getSendCtr >= 0'd25) begin
commandLine <=
shiftRegister = {shiftRegister[31:1], dataLine};
end
if (getSendCtr >= 0'd40) begin
getSendCtr <= 0;
FABINT <= 1;
end
end
endmodule
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