Commit 8e0c3d70 authored by tsharith's avatar tsharith
Browse files

WE HAVE EXTRUSION! ~.~

parent 73535fd7
...@@ -57,13 +57,13 @@ ENDLIST ...@@ -57,13 +57,13 @@ ENDLIST
LIST FileManager LIST FileManager
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf,actgen_cxf" VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874679" TIME="1555893534"
SIZE="2736" SIZE="2736"
PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf" PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl" VALUE "<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\coreparameters.v,tb_hdl"
STATE="utd" STATE="utd"
TIME="1555874679" TIME="1555893534"
SIZE="1284" SIZE="1284"
PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf" PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
IS_READONLY="TRUE" IS_READONLY="TRUE"
...@@ -152,7 +152,7 @@ IS_READONLY="TRUE" ...@@ -152,7 +152,7 @@ IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.200\MSS.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS\2.5.200\MSS.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874653" TIME="1555883767"
SIZE="945" SIZE="945"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
...@@ -170,97 +170,97 @@ IS_READONLY="TRUE" ...@@ -170,97 +170,97 @@ IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ACE\2.2.100\MSS_ACE.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ACE\2.2.100\MSS_ACE.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CCC\2.0.106\MSS_CCC.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CCC\2.0.106\MSS_CCC.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_CM3\1.0.200\MSS_CM3.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_COM\1.0.200\MSS_COM.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_COM\1.0.200\MSS_COM.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_DMA\1.0.101\MSS_DMA.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_DMA\1.0.101\MSS_DMA.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ENVM\2.3.200\MSS_ENVM.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_ENVM\2.3.200\MSS_ENVM.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="253" SIZE="253"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIC\1.0.101\MSS_FIC.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIC\1.0.101\MSS_FIC.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIO\1.0.203\MSS_FIO.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_FIO\1.0.203\MSS_FIO.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_GPIO\1.0.101\MSS_GPIO.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_GPIO\1.0.101\MSS_GPIO.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="253" SIZE="253"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_INTR\1.0.101\MSS_INTR.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_INTR\1.0.101\MSS_INTR.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="253" SIZE="253"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RESET\1.0.101\MSS_RESET.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RESET\1.0.101\MSS_RESET.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="254" SIZE="254"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RTC\1.0.100\MSS_RTC.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_RTC\1.0.100\MSS_RTC.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="252" SIZE="252"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_TIMER\1.0.100\MSS_TIMER.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_TIMER\1.0.100\MSS_TIMER.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="254" SIZE="254"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UART\1.0.101\MSS_UART.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UART\1.0.101\MSS_UART.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="253" SIZE="253"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UFROM\1.0.100\MSS_UFROM.cxf,actgen_cxf" VALUE "<project>\component\Actel\SmartFusionMSS\MSS_UFROM\1.0.100\MSS_UFROM.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="254" SIZE="254"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf" VALUE "<project>\component\work\DESIGN_FIRMWARE\DESIGN_FIRMWARE.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874649" TIME="1555888826"
SIZE="2374" SIZE="2374"
ENDFILE ENDFILE
VALUE "<project>\component\work\DESIGN_IO\DESIGN_IO.cxf,actgen_cxf" VALUE "<project>\component\work\DESIGN_IO\DESIGN_IO.cxf,actgen_cxf"
...@@ -270,13 +270,13 @@ SIZE="413" ...@@ -270,13 +270,13 @@ SIZE="413"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_Integration\SB_Integration.cxf,actgen_cxf" VALUE "<project>\component\work\SB_Integration\SB_Integration.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874682" TIME="1555893537"
SIZE="7263" SIZE="7263"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_Integration\SB_Integration.pdc,pdc" VALUE "<project>\component\work\SB_Integration\SB_Integration.pdc,pdc"
STATE="utd" STATE="utd"
TIME="1555874678" TIME="1555893533"
SIZE="1202" SIZE="1497"
PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf" PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf"
BEGIN_USE_CONSTRAINT BEGIN_USE_CONSTRAINT
TOOL_CONSTRAINT_TYPE="ideDESIGNER" TOOL_CONSTRAINT_TYPE="ideDESIGNER"
...@@ -286,41 +286,41 @@ IS_READONLY="TRUE" ...@@ -286,41 +286,41 @@ IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_Integration\SB_Integration.v,hdl" VALUE "<project>\component\work\SB_Integration\SB_Integration.v,hdl"
STATE="utd" STATE="utd"
TIME="1555874679" TIME="1555893534"
SIZE="19302" SIZE="19037"
PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf" PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf"
IS_READONLY="TRUE" IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\MSS_ACE_0\MSS_ACE_0.log,???" VALUE "<project>\component\work\SB_MSS\MSS_ACE_0\MSS_ACE_0.log,???"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555888826"
SIZE="31587" SIZE="31587"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
IS_READONLY="TRUE" IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\MSS_CCC_0\SB_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf,actgen_cxf" VALUE "<project>\component\work\SB_MSS\MSS_CCC_0\SB_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="479" SIZE="479"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\MSS_CCC_0\SB_MSS_tmp_MSS_CCC_0_MSS_CCC.v,hdl" VALUE "<project>\component\work\SB_MSS\MSS_CCC_0\SB_MSS_tmp_MSS_CCC_0_MSS_CCC.v,hdl"
STATE="utd" STATE="utd"
TIME="1555874650" TIME="1555883764"
SIZE="2879" SIZE="2879"
PARENT="<project>\component\work\SB_MSS\MSS_CCC_0\SB_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf" PARENT="<project>\component\work\SB_MSS\MSS_CCC_0\SB_MSS_tmp_MSS_CCC_0_MSS_CCC.cxf"
IS_READONLY="TRUE" IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc" VALUE "<project>\component\work\SB_MSS\MSS_ENVM_0\MSS_ENVM_0.efc,efc"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555888826"
SIZE="18054" SIZE="18054"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
IS_READONLY="TRUE" IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\mss_tshell.v,hdl" VALUE "<project>\component\work\SB_MSS\mss_tshell.v,hdl"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="12226" SIZE="12226"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
BEGIN_USE_CONSTRAINT BEGIN_USE_CONSTRAINT
...@@ -332,7 +332,7 @@ IS_READONLY="TRUE" ...@@ -332,7 +332,7 @@ IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc" VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
STATE="utd" STATE="utd"
TIME="1555874652" TIME="1555883766"
SIZE="184" SIZE="184"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
BEGIN_USE_CONSTRAINT BEGIN_USE_CONSTRAINT
...@@ -344,12 +344,12 @@ IS_READONLY="TRUE" ...@@ -344,12 +344,12 @@ IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\SB_MSS.cxf,actgen_cxf" VALUE "<project>\component\work\SB_MSS\SB_MSS.cxf,actgen_cxf"
STATE="utd" STATE="utd"
TIME="1555874654" TIME="1555888826"
SIZE="14032" SIZE="14032"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\SB_MSS.pdc,pdc" VALUE "<project>\component\work\SB_MSS\SB_MSS.pdc,pdc"
STATE="utd" STATE="utd"
TIME="1555874646" TIME="1555888826"
SIZE="1046" SIZE="1046"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
BEGIN_USE_CONSTRAINT BEGIN_USE_CONSTRAINT
...@@ -360,59 +360,59 @@ IS_READONLY="TRUE" ...@@ -360,59 +360,59 @@ IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\component\work\SB_MSS\SB_MSS.v,hdl" VALUE "<project>\component\work\SB_MSS\SB_MSS.v,hdl"
STATE="utd" STATE="utd"
TIME="1555874653" TIME="1555888826"
SIZE="21255" SIZE="21255"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
IS_READONLY="TRUE" IS_READONLY="TRUE"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration.adb,adb" VALUE "<project>\designer\impl1\SB_Integration.adb,adb"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888826"
SIZE="1775616" SIZE="1935360"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration.fdb,fdb" VALUE "<project>\designer\impl1\SB_Integration.fdb,fdb"
STATE="utd" STATE="utd"
TIME="1555874776" TIME="1555893672"
SIZE="81932" SIZE="80227"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration.ide_des,ide_des" VALUE "<project>\designer\impl1\SB_Integration.ide_des,ide_des"
STATE="utd" STATE="utd"
TIME="1555869127" TIME="1555888826"
SIZE="1431" SIZE="1522"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_compile_log.rpt,log" VALUE "<project>\designer\impl1\SB_Integration_compile_log.rpt,log"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555893618"
SIZE="30322" SIZE="30231"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_fp\projectData\SB_Integration.pdb,pdb" VALUE "<project>\designer\impl1\SB_Integration_fp\projectData\SB_Integration.pdb,pdb"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888826"
SIZE="82550" SIZE="88046"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_fp\SB_Integration.pdb,pdb" VALUE "<project>\designer\impl1\SB_Integration_fp\SB_Integration.pdb,pdb"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888826"
SIZE="82550" SIZE="88046"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_fp\SB_Integration.pro,pro" VALUE "<project>\designer\impl1\SB_Integration_fp\SB_Integration.pro,pro"
STATE="utd" STATE="utd"
TIME="1555869127" TIME="1555888498"
SIZE="2617" SIZE="2686"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_placeroute_log.rpt,log" VALUE "<project>\designer\impl1\SB_Integration_placeroute_log.rpt,log"
STATE="utd" STATE="utd"
TIME="1555874761" TIME="1555893658"
SIZE="14236" SIZE="14262"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_prgdata_log.rpt,log" VALUE "<project>\designer\impl1\SB_Integration_prgdata_log.rpt,log"
STATE="utd" STATE="utd"
TIME="1555874777" TIME="1555893673"
SIZE="1048" SIZE="1048"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\SB_Integration_verifytiming_log.rpt,log" VALUE "<project>\designer\impl1\SB_Integration_verifytiming_log.rpt,log"
STATE="utd" STATE="utd"
TIME="1555874766" TIME="1555893663"
SIZE="3262" SIZE="3262"
ENDFILE ENDFILE
VALUE "<project>\designer\impl1\spi_master.adb,adb" VALUE "<project>\designer\impl1\spi_master.adb,adb"
...@@ -432,28 +432,28 @@ SIZE="7780" ...@@ -432,28 +432,28 @@ SIZE="7780"
ENDFILE ENDFILE
VALUE "<project>\hdl\extruder_Drive.v,hdl" VALUE "<project>\hdl\extruder_Drive.v,hdl"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555893376"
SIZE="2694" SIZE="2399"
ENDFILE ENDFILE
VALUE "<project>\hdl\hotend_temp.v,hdl" VALUE "<project>\hdl\hotend_temp.v,hdl"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888826"
SIZE="6036" SIZE="6036"
ENDFILE ENDFILE
VALUE "<project>\hdl\PID.v,hdl" VALUE "<project>\hdl\PID.v,hdl"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888826"
SIZE="1921" SIZE="1921"
ENDFILE ENDFILE
VALUE "<project>\hdl\SPI_master.v,hdl" VALUE "<project>\hdl\SPI_master.v,hdl"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555890173"
SIZE="2574" SIZE="2574"
ENDFILE ENDFILE
VALUE "<project>\hdl\stepper.v,hdl" VALUE "<project>\hdl\stepper.v,hdl"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555893449"
SIZE="2687" SIZE="2831"
ENDFILE ENDFILE
VALUE "<project>\hdl\timer.v,hdl" VALUE "<project>\hdl\timer.v,hdl"
STATE="utd" STATE="utd"
...@@ -480,13 +480,13 @@ PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf" ...@@ -480,13 +480,13 @@ PARENT="<project>\component\Actel\DirectCore\CoreAPB3\4.1.100\CoreAPB3.cxf"
ENDFILE ENDFILE
VALUE "<project>\simulation\subsystem.bfm,sim" VALUE "<project>\simulation\subsystem.bfm,sim"
STATE="utd" STATE="utd"
TIME="1555874679" TIME="1555893534"
SIZE="705" SIZE="705"
PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf" PARENT="<project>\component\work\SB_Integration\SB_Integration.cxf"
ENDFILE ENDFILE
VALUE "<project>\simulation\test.bfm,sim" VALUE "<project>\simulation\test.bfm,sim"
STATE="utd" STATE="utd"
TIME="1555874651" TIME="1555888826"
SIZE="12569" SIZE="12569"
PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
...@@ -498,23 +498,23 @@ PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf" ...@@ -498,23 +498,23 @@ PARENT="<project>\component\work\SB_MSS\SB_MSS.cxf"
ENDFILE ENDFILE
VALUE "<project>\synthesis\SB_Integration.edn,syn_edn" VALUE "<project>\synthesis\SB_Integration.edn,syn_edn"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888826"
SIZE="1076259" SIZE="1174511"
ENDFILE ENDFILE
VALUE "<project>\synthesis\SB_Integration.so,so" VALUE "<project>\synthesis\SB_Integration.so,so"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888365"
SIZE="296" SIZE="319"
ENDFILE ENDFILE
VALUE "<project>\synthesis\SB_Integration_sdc.sdc,syn_sdc" VALUE "<project>\synthesis\SB_Integration_sdc.sdc,syn_sdc"
STATE="utd" STATE="utd"
TIME="1555861168" TIME="1555888365"
SIZE="530" SIZE="530"
ENDFILE ENDFILE
VALUE "<project>\synthesis\SB_Integration_syn.prj,prj" VALUE "<project>\synthesis\SB_Integration_syn.prj,prj"
STATE="utd" STATE="utd"
TIME="1555869127" TIME="1555888826"
SIZE="4167" SIZE="4535"
ENDFILE ENDFILE
VALUE "<project>\synthesis\spi_master.edn,syn_edn" VALUE "<project>\synthesis\spi_master.edn,syn_edn"
STATE="ood" STATE="ood"
...@@ -533,7 +533,7 @@ SIZE="401" ...@@ -533,7 +533,7 @@ SIZE="401"
ENDFILE ENDFILE
VALUE "<project>\synthesis\spi_master_syn.prj,prj" VALUE "<project>\synthesis\spi_master_syn.prj,prj"
STATE="utd" STATE="utd"
TIME="1555861225" TIME="1555869164"
SIZE="0" SIZE="0"
ENDFILE ENDFILE
ENDLIST ENDLIST
...@@ -548,24 +548,6 @@ VALUE "<project>\component\work\SB_Integration\SB_Integration.pdc,pdc" ...@@ -548,24 +548,6 @@ VALUE "<project>\component\work\SB_Integration\SB_Integration.pdc,pdc"
ENDLIST ENDLIST
LIST SynthesisConstraints LIST SynthesisConstraints
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc" VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"
VALUE "<project>\component\work\SB_MSS\mss_tshell_syn.sdc,sdc"