Commit 7c62d31c authored by kamako's avatar kamako
Browse files

Created ADNS header file

parent c9de7fab
#include <mss_spi.h>
#include <stdio.h>
#include <math.h>
#include "firmware.h"
#include "drivers/mss_gpio/mss_gpio.h"
#include "mss_timer.h"
const uint8_t REG_Product_ID =0x00;
const uint8_t REG_Revision_ID =0x01;
const uint8_t REG_Motion =0x02;
const uint8_t REG_Delta_X_L =0x03;
const uint8_t REG_Delta_X_H =0x04;
const uint8_t REG_Delta_Y_L =0x05;
const uint8_t REG_Delta_Y_H =0x06;
const uint8_t REG_SQUAL =0x07;
const uint8_t REG_Pixel_Sum =0x08;
const uint8_t REG_Maximum_Pixel =0x09;
const uint8_t REG_Minimum_Pixel =0x0a;
const uint8_t REG_Shutter_Lower =0x0b;
const uint8_t REG_Shutter_Upper =0x0c;
const uint8_t REG_Frame_Period_Lower =0x0d;
const uint8_t REG_Frame_Period_Upper =0x0e;
const uint8_t REG_Configuration_I =0x0f;
const uint8_t REG_Configuration_II =0x10;
const uint8_t REG_Frame_Capture =0x12;
const uint8_t REG_SROM_Enable =0x13;
const uint8_t REG_Run_Downshift =0x14;
const uint8_t REG_Rest1_Rate =0x15;
const uint8_t REG_Rest1_Downshift =0x16;
const uint8_t REG_Rest2_Rate =0x17;
const uint8_t REG_Rest2_Downshift =0x18;
const uint8_t REG_Rest3_Rate =0x19;
const uint8_t REG_Frame_Period_Max_Bound_Lower =0x1a;
const uint8_t REG_Frame_Period_Max_Bound_Upper =0x1b;
const uint8_t REG_Frame_Period_Min_Bound_Lower =0x1c;
const uint8_t REG_Frame_Period_Min_Bound_Upper =0x1d;
const uint8_t REG_Shutter_Max_Bound_Lower =0x1e;
const uint8_t REG_Shutter_Max_Bound_Upper =0x1f;
const uint8_t REG_LASER_CTRL0 =0x20;
const uint8_t REG_Observation =0x24;
const uint8_t REG_Data_Out_Lower =0x25;
const uint8_t REG_Data_Out_Upper =0x26;
const uint8_t REG_SROM_ID =0x2a;
const uint8_t REG_Lift_Detection_Thr =0x2e;
const uint8_t REG_Configuration_V =0x2f;
const uint8_t REG_Configuration_IV =0x39;
const uint8_t REG_Power_Up_Reset =0x3a;
const uint8_t REG_Shutdown =0x3b;
const uint8_t REG_Inverse_Product_ID =0x3f;
const uint8_t REG_Motion_Burst =0x50;
const uint8_t REG_SROM_Load_Burst =0x62;
const uint8_t REG_Pixel_Burst =0x64;
const uint8_t frame_size = 8;
const int ncs = MSS_GPIO_8; //F1
void start_hardware_timer(uint32_t period){
MSS_TIM1_init(MSS_TIMER_ONE_SHOT_MODE);
MSS_TIM1_load_immediate(period);
MSS_TIM1_start();
MSS_TIM1_enable_irq();
}
volatile char timerExpired=0;
void delay(uint32_t microseconds){
timerExpired=0;
start_hardware_timer(microseconds*100);
while(!timerExpired);
}
void Timer1_IRQHandler( void ){
timerExpired=1;
MSS_TIM1_clear_irq();
}
void adns_write_reg(unsigned char reg_addr, unsigned char data){
unsigned char bytes[2];
bytes[0]=reg_addr|0x80;
bytes[1]=data;
MSS_GPIO_set_output(ncs,0); //MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
// MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
MSS_SPI_transfer_frame( &g_mss_spi1, bytes[0] );
MSS_SPI_transfer_frame( &g_mss_spi1, bytes[1] );
delay(20);
// MSS_SPI_clear_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
MSS_GPIO_set_output(ncs,1); //MSS_SPI_clear_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
delay(100);
}
unsigned char adns_read_reg(unsigned char reg_addr){
unsigned char ret[1];
reg_addr=reg_addr&0x7f;
MSS_GPIO_set_output(ncs,0); //MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
MSS_SPI_transfer_frame( &g_mss_spi1, reg_addr );
delay(100);
ret[0]=MSS_SPI_transfer_frame( &g_mss_spi1, 0 );
delay(1);
MSS_GPIO_set_output(ncs,1); //MSS_SPI_clear_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
delay(19);
return ret[0];
}
void initADNS(){
MSS_SPI_init( &g_mss_spi1 );
MSS_SPI_configure_master_mode
(
&g_mss_spi1,
MSS_SPI_SLAVE_0,
MSS_SPI_MODE3,
MSS_SPI_PCLK_DIV_128,
frame_size
);
MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
MSS_GPIO_config(ncs, MSS_GPIO_OUTPUT_MODE);
MSS_GPIO_set_output(ncs,0); //MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
MSS_GPIO_set_output(ncs,1); //MSS_SPI_clear_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
//MSS_GPIO_set_output(ncs,1); //MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
adns_write_reg(REG_Power_Up_Reset,0x5a);
delay(50000);
adns_read_reg(REG_Motion);
adns_read_reg(REG_Delta_X_L);
adns_read_reg(REG_Delta_X_H);
adns_read_reg(REG_Delta_Y_L);
adns_read_reg(REG_Delta_Y_H);
adns_write_reg(REG_Configuration_IV,0x02);
adns_write_reg(REG_SROM_Enable,0x1d);
delay(10000);
adns_write_reg(REG_SROM_Enable,0x18);
data=REG_SROM_Load_Burst |0x80;
MSS_GPIO_set_output(ncs,0); //MSS_SPI_set_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 );
MSS_SPI_transfer_frame( &g_mss_spi1, data );
delay(15);
int c=0;
for(c=0;c<3070;++c){
MSS_SPI_transfer_frame( &g_mss_spi1, SROMA6[c] );
delay(15);
}
MSS_GPIO_set_output(ncs,1); //MSS_SPI_clear_slave_select( &g_mss_spi1, MSS_SPI_SLAVE_0 ); //firmware
delay(10000);
uint8_t laser_ctrl0;
data=0x1d;
laser_ctrl0=adns_read_reg(REG_LASER_CTRL0);
adns_write_reg(REG_LASER_CTRL0, (laser_ctrl0 & 0xf0) | 0x04 );
laser_ctrl0=adns_read_reg(REG_LASER_CTRL0);
uint8_t config=adns_read_reg(REG_Configuration_I);
adns_write_reg(REG_Configuration_I, (config&0b11000000)|0x29 );
}
short getX(){
volatile uint8_t XL;
volatile uint8_t XH;
XL = adns_read_reg(REG_Delta_X_L);
XH = adns_read_reg(REG_Delta_X_H);
return XL|(XH<<8);
}
short getY(){
volatile uint8_t YL;
volatile uint8_t YH;
YL = adns_read_reg(REG_Delta_Y_L);
YH = adns_read_reg(REG_Delta_Y_H);
return YL|(YH<<8);
}
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