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Commit 63000f59 authored by plyoung's avatar plyoung
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started hold states

parent 8e0c3d70
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SPI_Slave/spi_slave.v
View file @ 63000f59
......@@ -19,7 +19,10 @@ module spi_slave(
output data_stage,
output [31:0] fl_steps_remain,
output loco_update,
output reg [15:0] loco_excite
output loco_fin,
output fl_fin,
output reg [15:0] loco_excite,
output loco_int
);
......@@ -32,7 +35,7 @@ localparam Z_PERIOD = 8'h00,
FR_STEPS = 8'h24,
RL_STEPS = 8'h28,
RR_STEPS = 8'h2C;
reg [7:0] spi_addr;
//reg [5:0] spi_state;
......@@ -45,6 +48,7 @@ reg [31:0] z_period, loco_period;
reg [31:0] z_steps, fl_steps, fr_steps, rl_steps, rr_steps;
reg [15:0] z_excite;
reg z_update, loco_update;
reg loco_fin, loco_fin_prev;
wire [31:0] z_steps_remain, fl_steps_remain, fr_steps_remain, rl_steps_remain, rr_steps_remain;
wire z_ack, fl_ack, fr_ack, rl_ack, rr_ack;
......@@ -56,10 +60,14 @@ assign data_stage = (spi_state > 8) && (spi_state < 41);
assign addr_index = spi_state;
assign data_index = spi_state - 9;
assign loco_int = (loco_fin == 1'b1) && (loco_fin_prev == 1'b0);
// read address and write bit. Copy data to a temporary register
always@(negedge spi_clk)
begin
loco_fin_prev = loco_fin;
loco_fin = (fl_fin == 1'b1) && (fr_fin == 1'b1) && (rl_fin == 1'b1) && (rr_fin == 1'b1);
if(addr_stage)
begin
spi_addr[addr_index] <= mosi;
......@@ -208,7 +216,7 @@ begin
begin
loco_excite[data_index] <= spi_data;
end
else if(data_index == 31)
else if(data_index == 16)
begin
loco_update <= spi_data;
end
......
SPI_Slave/spi_slave.zip
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SPI_Slave/stepper.v
View file @ 63000f59
......@@ -19,24 +19,39 @@ module stepper(
reg [30:0] steps, steps_remain;
reg [3:0] motor_state, motor_next_state;
reg finished, finished_prev;
reg [3:0] finished_reg;
//reg finished, finished_prev;
reg direction;
assign int = finished & (~finished_prev);
//assign int = (finished_reg[3] == 1'b1) && (finished_reg[2] == 1'b0);
assign int = (finished_reg[0] == 1'b1) && (finished_reg[1] == 1'b0);
assign finished = finished_reg[3];
always@(posedge CLK)
begin
direction = signed_steps[31];
signed_steps_remain[31] <= direction;
if(direction)
// set initial conditions on reset
if(reset)
begin
steps = ~signed_steps + 1;
signed_steps_remain[30:0] <= ~steps_remain[30:0] + 1;
steps = 0;
direction = 0;
signed_steps_remain = 0;
end
// normal operation
else
begin
steps = signed_steps;
signed_steps_remain[30:0] <= steps_remain[30:0];
direction = signed_steps[31];
signed_steps_remain[31] <= direction;
if(direction)
begin
steps = ~signed_steps + 1;
signed_steps_remain[30:0] <= ~steps_remain[30:0] + 1;
end
else
begin
steps = signed_steps;
signed_steps_remain[30:0] <= steps_remain[30:0];
end
end
end
......@@ -44,81 +59,114 @@ timer motor_timer(CLK, period, period >> 1, , motor_clk, );
always@(posedge motor_clk)
begin
finished_prev = finished;
if(update)
begin
steps_remain = steps;
finished = 0;
ack = 1;
end
else if(steps_remain != 0)
begin
motor_state = motor_next_state;
steps_remain = steps_remain - 1;
finished = 0;
ack = 0;
end
else
begin
steps_remain = 0;
finished = 1;
ack = 0;
end
// set initial conditions on reset
if(reset)
begin
steps_remain = 0;
motor_state = 4'b0001;
finished_reg = 2'b11;
//finished = 1;
//finished_prev = 1;
ack = 0;
end
// normal operation
else
begin
finished_reg[3:1] = finished_reg[2:0];
//finished_reg[3] = finished_reg[2];
//finished_reg[2] = finished_reg[1];
//finished_reg[1] = finished_reg[0];
//finished_prev = finished;
if(update)
begin
steps_remain = steps;
finished_reg[0] = 0;
//finished = 0;
ack = 1;
end
else if(steps_remain != 0)
begin
motor_state = motor_next_state;
steps_remain = steps_remain - 1;
finished_reg[0] = 0;
//finished = 0;
ack = 0;
end
else
begin
steps_remain = 0;
finished_reg[0] = 1;
//finished = 1;
ack = 0;
end
end
end
always@(*)
begin
case(motor_state)
4'b0001 :
begin
if(direction)
motor_next_state = 4'b0010;
else
motor_next_state = 4'b1000;
if(~finished)
coils[3:0] = excitation[3:0];
else
coils[3:0] = 4'b0000;
end
4'b0010 :
begin
if(direction)
motor_next_state = 4'b0100;
else
motor_next_state = 4'b0001;
if(~finished)
coils[3:0] = excitation[7:4];
else
coils[3:0] = 4'b0000;
end
4'b0100:
begin
if(direction)
motor_next_state = 4'b1000;
else
motor_next_state = 4'b0010;
if(~finished)
coils[3:0] = excitation[11:8];
else
coils[3:0] = 4'b0000;
end
4'b1000:
begin
if(direction)
motor_next_state = 4'b0001;
else
motor_next_state = 4'b0100;
if(~finished)
coils[3:0] = excitation[15:12];
else
coils[3:0] = 4'b0000;
end
default:
begin
motor_next_state = 4'b0001;
coils[3:0] = 4'b0000;
end
endcase
// set initial conditions on reset
if(reset)
begin
motor_next_state = 4'b0001;
coils = 4'b0000;
end
// normal operation
else
begin
case(motor_state)
4'b0001 :
begin
if(direction)
motor_next_state = 4'b0010;
else
motor_next_state = 4'b1000;
if(~finished_reg[0])
coils[3:0] = excitation[3:0];
else
coils[3:0] = 4'b0000;
end
4'b0010 :
begin
if(direction)
motor_next_state = 4'b0100;
else
motor_next_state = 4'b0001;
if(~finished_reg[0])
coils[3:0] = excitation[7:4];
else
coils[3:0] = 4'b0000;
end
4'b0100:
begin
if(direction)
motor_next_state = 4'b1000;
else
motor_next_state = 4'b0010;
if(~finished_reg[0])
coils[3:0] = excitation[11:8];
else
coils[3:0] = 4'b0000;
end
4'b1000:
begin
if(direction)
motor_next_state = 4'b0001;
else
motor_next_state = 4'b0100;
if(~finished_reg[0])
coils[3:0] = excitation[15:12];
else
coils[3:0] = 4'b0000;
end
default:
begin
motor_next_state = 4'b0001;
coils[3:0] = 4'b0000;
end
endcase
end
end
endmodule
\ No newline at end of file
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