Altium

Design Rule Verification Report

Date:		12/1/2018
Time:		1:22:13 PM
Elapsed Time:		00:00:01
Filename:		C:\Users\hanse\Google Drive\Documents\School\Clubs\MER\Boards_Altium_11-20-2018\PCDC Control\PCDC_Control_Nov18th\PCDC_Control\PCDC_Control.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=0.254mm) (All),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Modified Polygon (Allow modified: No), (Allow shelved: No)	0
Width Constraint (Min=0.5mm) (Max=1mm) (Preferred=1mm) (InNet('PC_Stop'))	0
Width Constraint (Min=0.5mm) (Max=1mm) (Preferred=1mm) (InNet('ACC_ON'))	0
Width Constraint (Min=0.5mm) (Max=0.5mm) (Preferred=0.5mm) (All)	0
Width Constraint (Min=0.5mm) (Max=1mm) (Preferred=1mm) (InNet('GND'))	0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=0.178mm) (All)	0
Hole Size Constraint (Min=0.33mm) (Max=6.731mm) (All)	0
Hole To Hole Clearance (Gap=0.254mm) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All)	0
Silk To Solder Mask (Clearance=0.152mm) (IsPad),(All)	0
Silk to Silk (Clearance=0mm) (All),(All)	0
Net Antennae (Tolerance=0mm) (All)	0
Board Clearance Constraint (Gap=0mm) (All)	0
Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)	0
Total	0